Announcement

Collapse
No announcement yet.

ECC Support for Intel Cascade Lake chipsets

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • ECC Support for Intel Cascade Lake chipsets

    Hi everyone,
    I was waiting for memtest86 v9.4 to see if ECC support for Intel Cascade Lake chipsets (C621), would have been added but it seem to be missing.
    But even with the new version I am still getting ECC enable: N/A (unknown)

    Is there any chance to see this feature supported in the future versions?

    Thanks.
    Paul

  • #2
    Can you Email or post the MemTest86 debug log for that machine.

    Comment


    • #3
      Hi David,
      thank you for your answer.

      The CPU is a Xeon W-3245, which should be a Cascade Lake
      https://ark.intel.com/content/www/it...-3-20-ghz.html

      But it seems to be detected as a Sky Lake and the ECC memory is not seen.
      Windows and Linux shows the ECC is used.

      Thanks.
      Paul
      Attached Files

      Comment


      • #4
        Thanks for the logs.

        We're in the process of obtaining the necessary datasheets for Cascade Lake, and should be able to add ECC support for the next release.

        Comment


        • #5
          Originally posted by Paul2112 View Post
          Hi David,
          thank you for your answer.

          The CPU is a Xeon W-3245, which should be a Cascade Lake
          https://ark.intel.com/content/www/it...-3-20-ghz.html

          But it seems to be detected as a Sky Lake and the ECC memory is not seen.
          Windows and Linux shows the ECC is used.

          Thanks.
          Paul
          We made some changes to support Cascade Lake ECC.

          Can you give this build a try:
          https://www.passmark.com/temp/memtes...-v9.4.1001.zip

          Comment


          • #6
            Hi David,
            I tested the proposed build. It has been necessary to disable Secure Boot, but I guess it was something expected.
            I believe now the ECC RAM is recognized, however, the memory controller seems to be reported as a skylake rather than a cascade lake.
            Is it something which is more convenient for your implementation or actually the platform is a skylake?
            Thanks.
            Paul
            Attached Files

            Comment


            • #7
              Hello PassMark Team,
              I encountered the same problem with one of our servers. We have a Cascadelake CPU (Xeon Gold 5220) with ECC RAM, but in memtest86 v10.5 ECC shows as unavailable.
              Could you please upload a patched version again? Iif you need more information let me know.
              Thanks in advance​

              Comment


              • #8
                Originally posted by EDV Team View Post
                I encountered the same problem with one of our servers. We have a Cascadelake CPU (Xeon Gold 5220) with ECC RAM, but in memtest86 v10.5 ECC shows as unavailable.


                Can you Email or post the MemTest86 debug log for that machine?

                Comment


                • #9
                  Originally posted by EDV Team View Post
                  Hello PassMark Team,
                  I encountered the same problem with one of our servers. We have a Cascadelake CPU (Xeon Gold 5220) with ECC RAM, but in memtest86 v10.5 ECC shows as unavailable.
                  Could you please upload a patched version again? Iif you need more information let me know.
                  Thanks in advance​
                  Can you give this build a try:
                  https://www.passmark.com/temp/memtes...-10.5.1012.zip

                  Comment


                  • #10
                    Hi Keith,

                    I'm sorry for my late response, I ran some tests overnight and your build worked! Thank you very much.

                    Is the Cascade Lake support generally not build into memtest86 or was this a system specific problem?
                    It would be great if this fix would find its way into the next memtest86 release, so others could also benefit from it.

                    Best regards

                    Click image for larger version

Name:	mt86Screen-20230728-065240.png
Views:	140
Size:	42.1 KB
ID:	55575

                    Comment


                    • #11
                      Some of these Xeon CPUs are very rare and expensive. And new code needs to be written for each CPU family (as for some stupid reason Intel can't keep the interface the same). Plus to a large extend many of the details are secret and not in public documents.

                      So it isn't easy to get a sample for testing for many of these CPUs.

                      All new additions will end up in the public release. This will go into a V10.6 release.

                      Comment

                      Working...
                      X