MemTest86 v7.0 Beta 1 (2016-07-20 Update - Beta testing is now closed)

[keith]

(July 20/2016 Update) MemTest86 v7.0 has been officially released. As a result, MemTest86 v7.0 beta testing period is now over. Thank you to our beta testers for the bug reports and feedback.


Downloads
(July 20/2016 Update) MemTest86 v7.0 Pro and Site Edition can now be purchased from our sales page. As usual, the Free Edition is available for download on the normal MemTest86 download page. Beta downloads are no longer available.

New Features

• Row Hammer Test (Test 13) now uses double-sided hammering and random data patterns in an attempt to expose more RAM modules susceptible to disturbance errors. During our testing we observed double sided hammering was effective at high frequencies, but at lower frequencies single sided hammering was more effective. So feedback on this would be good.
• PXE network boot is now fully supported. Configuration file can now be obtained from the server. Report files can also be uploaded to the server. Logging is unavailable.
• Memory tests are run in Parallel CPU mode by default, if supported by the UEFI firmware. Running in parallel mode significantly decreases the test time as compared to running in single CPU mode and should also help to detect more errors faster. This was made possible after developing a work around for UEFI BIOS bug that prevented multi-threading on some machines.
• Added 'HAMMERPAT' config file parameter to specify the data pattern to use for the row hammer test. By default, random data patterns are used.
• Added 'HAMMERMODE' config file parameter to specify whether to use single or double sided hammering. By default, double-sided hammering is used.
• Added 'CPULIST' config file parameter to specify a subset of available CPUs to enable for the memory tests.
• Added 'BGCOLOR' config file parameter to specify the background colour to use
• Added Portuguese translations
• <We are hoping to add to this list before the final release>

Fixes/Enhancements

• Added ECC support for different revisions of Intel Skylake memory controllers
• Fixed ECC detection on Intel Broadwell-H chipsets
• Changed how ECC errors are detected on Broadwell chipsets
• Changed how ECC errors are detected on Atom C2000 chipset
• Added SMBUS (SPD) support for Intel Broxton
• Added SMBUS (SPD) support for Intel Airmont
• Reduced the number of iterations for the Modulo 20 Test (Test 9) to decrease the test time
• Reduced the number of addresses to be hammered for the Row hammer Test (Test 13) to decrease the test time
• When no tests are completed, the test report now displays "N/A" as oppose to "PASS"
• Speeds greater than 10000MB/s are converted to GB/s when displaying memory/cache speeds in the test screen

How to report problems

Either make a post here in the forum, or send us an email at the address listed on our contact page. When reporting an error please provide as much details as possible. If you are running on a USB drive, there should be a log file that has been generated in the EFI/BOOT directory called MemTest86.log. Sending us this will be of great help. Additionally a photograph of the problem would also be useful if possible/applicable.

[Nano]

Hi Keith,

When can we expect the official release of Memtest 86 V7.0..

Thanks.

[keith]

Before the official release of v7.0, we plan to release a few more beta versions with incremental roll-out of new features.

There is no exact date but it won't be for at least a couple months.

[karakarga07]

At the new version there is more place necessary for CPU cores. I have Xeon E5-2695 v2, 12/24 cores. The CPU: rank starts with and goes 0123456789ABCDEFGHIJKLMN for total number of cores. The newest E7-8890 v4 processor has 24/48 cores.

I wonder, how to fit and manage this, because English alphabet has 26 caracters. 10+26=36 maximum characters, but 48 characters necessary!

[keith]

Due to the limited amount of screen space, only the first 31 core/thread states are shown.

[patpat]

PXE bug

When PXE booting i.e. BOOTX64.EFI the application try to retrieve 2 files
unifont.bin
mt86.cfg
"always" from the TFTP "root directory"; not good.

This causes lot of problems for people using multi-asset PXE servers like Serva. The way it is now forces us to:

1. Have only one mt86.cfg in the PXE repository.
2. Add asset components out of the asset head directory.

Solution:
There are 2 ways to pass the TFTP location information to BOOTX64.EFI

1. BOOTX64.EFI command line parameter.
   i.e. Serva would boot with:
   
   kernel_efi64 = /NWA_PXE/$HEAD_DIR$/BOOTX64.EFI
   append_efi64 = path=/NWA_PXE/$HEAD_DIR$
2. BOOTX64.EFI looking where was booted from on the PXE stack
   Serva would boot with:
   
   kernel_efi64 = pxechn.c32
   append_efi64 = /NWA_PXE/$HEAD_DIR$/BOOTX64.EFI

The first option is very simple and can be added with 3 lines of code for TFTP, it could also handle HTTP or even FTP.

The second option requires knowing a bit the UEFI PXE stack but can be easily done.

Once BOOTX64.EFI has the starting path it retrieves i.e.
/NWA_PXE/Memtest/mt86.cfg
instead of just
mt86.cfg


I think PXE users would greatly benefit from fixing this issue.
If you guys need help on this please contact me by e-mail

Best,
Patrick

[keith]

Thanks for the feedback.

We'll look into making this change. It would be great if you are able to provide any assistance in testing new builds. If possible, can you send an e-mail so that we can be in contact.

[patpat]

Thanks for the feedback.

We'll look into making this change. It would be great if you are able to provide any assistance in testing new builds. If possible, can you send an e-mail so that we can be in contact.

Sure; I've already sent an e-mail.

Best,
Patrick