Test Memory speed per access step size

[brod9gnik]

Thank u, so in time answer, 1 hour to exam

[David (PassMark)]

It is complex to fully explain it.

CPUs (and motherboard, RAM & cache) are designed to read at least 4 bytes at a time. Further they are optimised to read sequentially through RAM. Or if not sequentially, then optimised to read values close to the last value read. e.g in the same memory row.

So reading 1 byte at a time tends to be slow. But reading at 4 bytes intervals tends to be quick. As the distances between memory accesses get larger, the system gets slower.

Background reading:
http://en.wikipedia.org/wiki/Locality_of_reference
http://en.wikipedia.org/wiki/CPU_cache
http://en.wikipedia.org/wiki/Prefetch_buffer

[brod9gnik]

That would be the most efficient step size for your hardware.

i need know why it most efficient.
I have such question at examination

i have Pentium Dual-Core E5300 2.6Ghz
L1 Data cache 2 x 32 KB
L2 1 x 2 MB

2 x 2GGb DDR2 SDRAM

[David (PassMark)]

That would be the most efficient step size for your hardware.

[brod9gnik]

i need help, guys, why peak is reached on the second step size?