pass 1 hammer rate of hammer test in memtest v6.2 ?

[lovemudddee]

Hi all,
According to information of v6.2 released, Hammer Test perform 2 potential passes.
Row pairs are hammered at the maximum hammer rate (ie. no delays between each row pair hammer) in Pass 1.
I don't understand what is 'the maximum hammer rate'.
How many repetitions of each Row opening/closing of Memtest v6.2 (Hammer Test)?
Thanks a lot.

[David (PassMark)]

You can find the detail in the MemTest86 release history.

[lovemudddee]

Hi David,
Thank you for your response.
I only find some information about hammer in release history as below, but i still confuse.
Has it exact number about hammer count of pass 1 in v6.2 ?
thank you.

v6.2
Shortened the test time for Hammer Test (Test 13) by reducing the total number of hammers per row address pair

v6.1
Fixed the progress indicator for Test 13 (Row hammer test) to be more linear
Reduced the test time for Test 13 (Row hammer test)

v6.0
New "Hammer Test" for detecting disturbance errors caused by charge leakage when repeatedly accessing addresses in the same memory bank but different rows in a short period of time.

[David (PassMark)]

Read the page again, right at the top. Starting with the text, "Row pairs are hammered at a lower hammer rate (200K per 64ms, as determined by memory vendors......."

[lovemudddee]

Hi David,

Due to the high number of failures reported for the Hammer Test (Test 13), the algorithm was revised to perform 2 potential passes:

1. Row pairs are hammered at the maximum hammer rate. (ie. no delays between each row pair hammer)
   
2. Row pairs are hammered at a lower hammer rate (200K per 64ms, as determined by memory vendors as the worst case scenario)

"Row pairs are hammered at a lower hammer rate (200K per 64ms)" --> Pass 2 of hammer test.
But my question is pass 1 (hammered at the maximum hammer rate).
Because errors are detected in first pass on my module but not the second pass.
So, i need to know how many repetitions of hammer test in Pass 1.
Thank you.

[keith]

The maximum hammer rate is the fastest rate your system can possibly read the address row pairs. There is no set value as it depends on the system configuration itself such as the CPU, memory controller, DIMM configuration, BIOS settings, etc.

In contrast to the lower hammer rate of the second pass, there is a small delay when reading the row pairs in order to achieve 200K per 64ms; there is no such delay in the first pass.

[lovemudddee]

Hi Keith,
Thank you for your response.
I have another question.
Whether all of row pairs are hammered in first pass then perform second pass, or one of row pairs perform first pass and second pass then change another row pairs?
Thank you so much.

[keith]

Row pairs are hammered in segments of the entire address range. The second pass is only performed if errors are detected in the first pass (ie. if no errors are detected, the second pass is never performed). Once errors are detected, the second pass (lower hammer rate) is performed for the remainder of the test.

[lovemudddee]

thank you for your help.

[lovemudddee]

I have a suggestion. Whether it could customize hammer rate by user in next revision ?

[David (PassMark)]

It might not be exactly what you want, but the configuration file has the REPORTNUMWARN setting that allows all the warnings to be listed out in the report.

[lovemudddee]

Because everyone has different guarantee for hammer test.
If it can customize for hammer rate by themself, they can define pass or fail for hammer test.
(e.g. If i want to know my module whether it pass 300k hammer rate, i can set 300k for hammer rate to test my module.)
thank you.

[mike@arnoldgauge.com]

Hi all,

I'm a bit confused by the hammer-testing, it doesn't seem to be a straightforward test. Do these results indicate a pass or a fail?

[David (PassMark)]

Mike,

Read this information on the hammer test to start with.

Basically, there was an memory error, but your error correcting ECC RAM detected it and corrected it. So it would have been a 1 bit error.

If it was a 2bit or greater error, the ECC ram could not have fixed it and MemTest86 would have reported a warning or error as the value in RAM would have been corrupted.

So it was a fail, that the ECC ram turned into a pass. Unless you consider corrected errors to be a fail. It is a matter of opinion and how much risk you want to take on.

[mike@arnoldgauge.com]

Thanks for the info!

I'll at least identify and likely discard the offending chip. If it was a workstation I wouldn't care, but this is a FreeNAS server and I'd rather not deal with an outage or potential data corruption.

The link was helpful, but I do have a quick follow-up question. I understand the ECC will identify and correct single-bit errors. The OS (FreeBSD in my case) won't be negatively affected.

What happens in a two-bit error? I understand the error can't be corrected, but does the server detect the error and notify the OS to retry and/or fail gracefully?